changed design as per your input, but still the output voltages are seems to be not proper,
when there is logic HIGH i.e. If I input 24V, and when I probe at out_plus, it is 24V and at out_minus it is 12V
when there is logic LOW i.e. if I input 0V, out_plus and out_minus will give 24V? can you explain this behaviour
when there is logic HIGH i.e. If I input 24V, and when I probe at out_plus, it is 24V and at out_minus it is 12V
when there is logic LOW i.e. if I input 0V, out_plus and out_minus will give 24V? can you explain this behaviour
Statistics: Posted by smarty — Fri May 10, 2024 11:15 am