oh, may I ask another question.Other than having one of aBUGSworstnightmare's dev boards, I have no significant information or experience for these TI chips.
4 lane DSI can have one foible that being 3 bytes per pixel, splitting across 4 lanes means that unless the width is a multiple of 3 the amount of data sent on each lane can vary as it splits at a byte level between the lanes. That shouldn't be an issue with 1920 though.
Due to the integer divide on the DSI PLL, you will generally need to use an external clock on these devices. Trying to lock off the DSI clock when it's not at the pixel rate will cause issues.
(1) keep clock-frequency 140M in devicetree, which the refresh rate is 60hz, actually in kernel driver the real clock is 166M or sometimes 187.5M, and the horizonal porch is extended to fill the more clock.
(2) keep clock-frequency 125M(or other definite number), which the adjusted clock in kernel driver is equals to 125M too. then no need to extend the horizonal porch.
compared between these two ways, which way do you think is more stable?
for example, my panel timing is horizonal pixel 2100, in which active is 1920, porch/sync is 60 60 60, and vertical active 1080, vertical porch/sync is 12 12 12. and the recommended LVDS clock is 2100 x 1116 x 24bpp x 60hz = 140Mhz.
as (1), I set 140Mhz in devicetree, but the chip can't generate the clock precisely, so the real clock may be 166Mhz, and filled by more porches. so finally the horizonal pixel is 2490, in which active is 1920, porch/sync 190 190 190.
advantage: the refresh rate is 60hz.
disadvantage: the real lvds clock is higher, and more porch than recommended in TI handbook.
as (2), I set 125Mhz in devicetree, and fortunately the hardware can generate the clock frequency, so finally the horizonal pixel is still 1920+60+60+60=2100, but the refresh rate is only 54hz.
advantage: porch is the same value as recommended in n TI handbook.
disadvantage: lower lvds clock and lower refresh rate.
which way is better?
thank you
Statistics: Posted by dcrane — Tue Apr 29, 2025 2:28 am