Just to throw out another possibility, if you have the spare pins, XMOS came up with a software-driven interface to SDRAM which “costs” 20 pins using a little hardware for a 16-bit memory interface that could probably be adapted to PIO - see https://github.com/xmos/lib_sdram
Don’t be scared of the 500 MHz requirement, they clock-divide amongst cores, so a “500MHz” chip actually runs a minimum of 4 cores at 125MHz each. 125MHz is the top speed available, and the library can handle a 62.5MHz clock rate, so the RP2350 ought to handle it fine.
With a little finagling and some latches, you could probably reduce it to an 8-bit bus + a couple of controls and get that cost down to 13 or 14 pins. You wouldn’t have direct memory access per-se though, you’d have to write sdram_read() and sdram_write() functions. Still, it’d give you lots of RAM![:)]( "Smile")
Don’t be scared of the 500 MHz requirement, they clock-divide amongst cores, so a “500MHz” chip actually runs a minimum of 4 cores at 125MHz each. 125MHz is the top speed available, and the library can handle a 62.5MHz clock rate, so the RP2350 ought to handle it fine.
With a little finagling and some latches, you could probably reduce it to an 8-bit bus + a couple of controls and get that cost down to 13 or 14 pins. You wouldn’t have direct memory access per-se though, you’d have to write sdram_read() and sdram_write() functions. Still, it’d give you lots of RAM
Statistics: Posted by ThrudTheBarbarian — Sat Jun 07, 2025 3:10 pm