Look here: viewtopic.php?t=375975&start=25#p2307164
Could be this, XIP cache is optimized for running code, and is working in short bursts:
Could be this, XIP cache is optimized for running code, and is working in short bursts:
I think DMA can do more.The number of SCK cycles issued for each access depends on the access size, which varies between one byte and one
cache line. For example, an uncached one-byte read by a processor will fetch exactly one byte of data over the QSPI bus,
to avoid wasting time fetching unwanted data. Cache misses are always issued as 64-bit QSPI transfers.
Statistics: Posted by gmx — Tue Jul 29, 2025 11:52 pm