Advanced users • Re: RP1 PLLs missing documentation

that macro is relative to this:

Code:

rp1->msix_cfg_regs = ioremap(rp1_io_to_phys(rp1, RP1_PCIE_APBS_BASE), 0x1000);

which is the offset from the start of the main (MM)IO BAR, 0x108000

Yea and adding that together gives 0x40108000, which is the start of the PCIe config registers. This address refers to the first register in it, which is the DBI register I mentioned earlier (see also "6.1. PCIe endpoint configuration registers" from RP1 data sheet). Now the macro, does this
And the +0x8 is exactly the offset to the MSIX_CFG_0 register in the PCIe controller registers. Now the strange part, which brings me back to my 3 questions, is that the macro is used here https://github.com/raspberrypi/linux/bl ... /rp1.c#L96 like that
So if the define "REG_SET" would be about atomic register access (which the name might suggest), it should be 0x2000, but in fact it is 0x800. Meaning those writes will land somewhere 0x40108808 + hwirq*4 ... and at least the RP1 data sheet does not give any info what is there to be found. ... Maybe that is where the DBI data could be written to 0x40108800? Hence my 3 questions

Statistics: Posted by wolfre — Mon Aug 25, 2025 2:48 pm

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