I see the guthub issue has got very busy...
For the first question, none of those. The IOMMUs are close to SDRAM. They operate on uncached memory and pay no attention to protection flags.*
For the PCIe stuff I will have to consult jdb or PhilE.
*I'm simplifying again. Addresses above 64GB can be routed back through the VPU L2 cache. This is not coherent with ARM caches and you basically never want to do this. Also on C1 (but not D0) there's a separate memory protection block downstream of the IOMMUs, which we have never tried to use.
For the first question, none of those. The IOMMUs are close to SDRAM. They operate on uncached memory and pay no attention to protection flags.*
For the PCIe stuff I will have to consult jdb or PhilE.
*I'm simplifying again. Addresses above 64GB can be routed back through the VPU L2 cache. This is not coherent with ARM caches and you basically never want to do this. Also on C1 (but not D0) there's a separate memory protection block downstream of the IOMMUs, which we have never tried to use.
Statistics: Posted by njh — Mon Sep 08, 2025 9:05 am