I wondered as well, there is a hint in RP2350 datasheet:Also, why are the INSTR_MEM0 to INSTR_MEM31 registers write-only?
I can only speculate, but note that those registers are really a RAM with (currently) 4 read ports and 1 write port (since each SM needs to read an instruction from the RAM on every clock cycle, plus the port to write it from the ARM side). Adding another read port would probably add significant silicon cost and/or performance impact.
Register files are actually regular flip-flops combined with a lot of muxes to do the read addressing and a ton of wires/traces.11.2.8. Interactions between state machines
Instruction memory is implemented as a 1-write, 4-read register file, allowing all four state machines to read an
instruction on the same cycle without stalling.
They are very fast but have very complex/dense routing.. That's my guess why they didn't add a fifth reading port for CPU.
Below just an idea of 1-write, 2-read register file:
Statistics: Posted by gmx — Fri Sep 12, 2025 12:42 am