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Interfacing (DSI, CSI, I2C, etc.) • Re: Question about FSLEN Support on Raspberry Pi 5 DWC-I²S

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On the Designware I2S peripheral, the "word select" line (frame sync) has a fixed high/low duration of 16/24/32 cycles. PIO could be used to construct an arbitrary I2S bitstream, but it would run off the system clock and be a fractional division of 200MHz unless the codec generated the required clock.
Hello, thank you for your reply.

I apologize for the delay—I was checking the differences with the Raspberry Pi 4 before following up.
On the Raspberry Pi 4B+, configuring the device tree with the CPU DAI set to the DSP_A format causes the bcm2835-i2s CPU driver to adjust the frame_length_sync, and TDM operates in short sync mode.

device tree example:

Code:

...simple-audio-card,format = "dsp_a";...
bcm2835-i2s.c

Code:

static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,                                 struct snd_pcm_hw_params *params,                                 struct snd_soc_dai *dai){    ...    switch (format) {        case SND_SOC_DAIFMT_DSP_A:            data_delay = 1;            framesync_length = 1;            frame_start_falling_edge = false;            break;        ...    }    mode |= BCM2835_I2S_FSLEN(framesync_length);    ...}
However, on the Raspberry Pi 5, configuring the device tree in the same way does not result in short sync operation, and I cannot find any place to adjust this setting.

Has this feature been removed with the change of model, or does the functionality still exist but has not yet been supported in software?

Additionally, aside from using PIO to generate the custom timing, is there any other way to achieve short sync operation on the Raspberry Pi 5?

Statistics: Posted by Umagon — Tue Sep 30, 2025 2:09 am



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