General • Re: RP2350B - IRQ latency

taking snapshots to a local variable still takes precious clocks,

Can use two of processor's registers (can reserve some from inline assembly), or in case of emergency, some tightly coupled registers (like interpolator).

XIP cache misses are stalling bus access, so most probably the interrupt is stalled too.
See a similar discussion: viewtopic.php?t=339945

Re: Interrupt while stalled on XIP fetch

08 Sep 2022, 15:09
It does not abandon an ongoing bus transaction, so it will affect latency. The only thing it will abandon is the rest of a multi-word intstruction (ldima/stmia/push/pop)

P.S.I would use the other core to serve critical interrupts, it can avoid lengthy stalls. If small enough, it can run entirely from scratch memory (the stack is also there).

Statistics: Posted by gmx — Wed Nov 05, 2025 11:27 pm

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