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SDK • Pico PIO IN read timing

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Hi,

I'm working on a PIO audio TDM driver (32 bits x 8 slots, 48kHz audio sample rate, SYSCLK = 147.6 MHz).

I need to read the input data on a particular clock edge, which is side-set.

Is the 'in' data clocked at the start of the instruction cycle or the end?

The code, as it stands, assumes the start (plus a SYSCLK cycle for the input synchronizer).

I note that the PIO I2S master example turns off the input synchronizers. Should I do this to increase the data input setup margin?

The bit rate is around 12.5MHz (40 nS per phase) and the data setup time from the CODEC is a bit less than 10nS, giving around 30nS data ready to data read set up time.

Thanks in advance.

Code:

; TI (e.g. TLV320AIC3104) standard: BCLK + WCLK rise together. Data starts on WCLK rising.; PIO clock at 4 x BCLK period (2 cycles per BCLK phase).program pio_tdm_inout.side_set 2   ; 0 = bclk, 1 = wclk; The C code should place (number of bits * channels - 1) in Y and update SHIFTCTRL; to be 32 (as per the TDM specs);                           +----- WCLK;                           |+---- BCLK    ; First bit out and WCLK rises at start of new frame    out pins, 1      side 0b11  [1] ; Output (at start of instruction cycle) changes on rising edge       in pins, 1       side 0b10      ; Sample input (at start of instruction cycle) before falling edge     mov x, y         side 0b10  bitloop:    out pins, 1      side 0b01 [1]     in pins, 1       side 0b00    jmp x-- bitloop  side 0b00     ; Loop back to the beginning

Statistics: Posted by palmerr23 — Mon Jan 26, 2026 3:41 am



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