Running (potentially) long-running evaluation code in an ISR is a bad idea.What I mean by unstable is that the PWM generated on core1 seems to slow down or speed up depending on what is being displayed on core0.
The Bytebeat class evaluates a mathematical formula represented as a string and returns a result as an integer. This result allows me to modulate the duty cycle of the generated PWM and produce bytebeat.
I suspect that the formula evaluation is relatively heavy, but it’s odd that its performance is impacted by what core0 is doing. Isn’t core1 supposed to run independently?
The cores are independent, but your code is obviously doing something that makes them wait on each other for some reason or another. One way of accidentally creating such a situation is by contention of an external-to-the-cores resource such as the flash memory.
But that's all just guessing without being able to look at the code that is actually being run on the 2nd core.
Statistics: Posted by Tharre — Thu Jun 05, 2025 2:28 pm