i was messing with pio before it was officially available, and also ran into troublesTypical per-channel read bandwidth is expected to be 500-600Mbs, and write bandwidth 2Gbps.
one issue, is that the DMA block has a 128bit bus, clocked at 100mhz
however, the PIO fifo is on a 32bit bus, so 3/4ths of your bandwidth is already gone
from my notes, i think i was able to get ~530mbit of rx performance back in 2024-02-16, but it was dropping random samples
i have since redone some of that code using the new piolib, but it isnt getting anywhere near as much performance, and even 530mbit wasnt enough for my original goal
edit:
https://github.com/cleverca22/libsigrok ... 8a3f99731a
this changeset configures sigrok and pulseview, so it can use PIO as a logic analyzer
Statistics: Posted by cleverca22 — Wed Aug 06, 2025 11:57 pm