In the cold light of day the problem is obvious - DMA channels 0 & 1 have maximum burst sizes of 8, not 4, so a FIFO threshold of 4 can lead to underflow (or overflow for a TX).
There's a kernel Pull Request (https://github.com/raspberrypi/linux/pull/7190) that always sets the PIO FIFO thresholds based on the DMA burst size. You will be able to install a trial build in about half an hour by running "sudo rpi-update pulls/7190" (after first checking the caveats - https://github.com/raspberrypi/rpi-upda ... le#caveats).
There's a kernel Pull Request (https://github.com/raspberrypi/linux/pull/7190) that always sets the PIO FIFO thresholds based on the DMA burst size. You will be able to install a trial build in about half an hour by running "sudo rpi-update pulls/7190" (after first checking the caveats - https://github.com/raspberrypi/rpi-upda ... le#caveats).
Statistics: Posted by PhilE — Thu Jan 08, 2026 12:26 pm